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LTC2242-10 10-Bit, 250Msps ADC FEATURES
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DESCRIPTION
The LTC(R)2242-10 is a 250Msps, sampling 10-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2240-10 is perfect for demanding communications applications with AC performance that includes 60.5dB SNR and 78dB SFDR. Ultralow jitter of 95fsRMS allows IF undersampling with excellent noise performance. DC specs include 0.4LSB INL (typ), 0.2LSB DNL (typ) and no missing codes over temperature. The digital outputs can be either differential LVDS, or single-ended CMOS. There are three format options for the CMOS outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. A separate output power supply allows the CMOS output swing to range from 0.5V to 2.625V. The ENC+ and ENC - inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *LTC2220-1, LTC2220, LTC2221, LTC2230, LTC2231 are 3.3V parts.
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Sample Rate: 250Msps 60.5dB SNR 78dB SFDR 1.2GHz Full Power Bandwidth S/H Single 2.5V Supply Low Power Dissipation: 740mW LVDS, CMOS, or Demultiplexed CMOS Outputs Selectable Input Ranges: 0.5V or 1V No Missing Codes Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Data Ready Output Clock Pin Compatible Family 250Msps: LTC2242-12 (12-Bit), LTC2242-10 (10-Bit) 210Msps: LTC2241-12 (12-Bit), LTC2241-10 (10-Bit) 170Msps: LTC2240-12 (12-Bit), LTC2240-10 (10-Bit) 185Msps: LTC2220-1 (12-Bit)* 170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)* 135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)* 64-Pin 9mm x 9mm QFN Package
APPLICATIONS
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Wireless and Wired Broadband Communication Cable Head-End Systems Power Amplifier Linearization Communications Test Equipment
TYPICAL APPLICATION
2.5V VDD REFH REFL FLEXIBLE REFERENCE 0.5V TO 2.625V OVDD D9 * * * D0 85 80 75 SFDR (dBFS) 70 65 1V RANGE 60 2V RANGE 55 OGND CLOCK/DUTY CYCLE CONTROL
224210 TA01
SFDR vs Input Frequency
+
ANALOG INPUT INPUT S/H
-
10-BIT PIPELINED ADC CORE
CORRECTION LOGIC
OUTPUT DRIVERS
CMOS OR LVDS
50 45 40 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
224210 G11
ENCODE INPUT
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LTC2242-10 ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Notes 1, 2)
PIN CONFIGURATION
TOP VIEW 64 GND 63 VDD 62 VDD 61 GND 60 VCM 59 SENSE 58 MODE 57 LVDS 56 OF+/OFA 55 OF-/DA9 54 D9+/DA8 53 D9-/DA7 52 D8+/DA6 51 D8-/DA5 50 OGND 49 OVDD AIN+ 1 AIN+ 2 AIN- 3 AIN- 4 REFHA 5 REFHA 6 REFLB 7 REFLB 8 REFHB 9 REFHB 10 REFLA 11 REFLA 12 VDD 13 VDD 14 VDD 15 GND 16 65 48 D7+/DA4 47 D7-/DA3 46 D6+/DA2 45 D6-/DA1 44 D5+/DA0 43 D5-/DNC 42 OVDD 41 OGND 40 D4+/DNC 39 D4-/CLKOUTA 38 D3+/CLKOUTB 37 D3-/OFB 36 CLKOUT+/DB9 35 CLKOUT-/DB8 34 OVDD 33 OGND UP PACKAGE 64-LEAD (9mm x 9mm) PLASTIC QFN EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB TJMAX = 150C, JA = 20C/W
Supply Voltage (VDD) ...............................................2.8V Digital Output Ground Voltage (OGND) ........ -0.3V to 1V Analog Input Voltage (Note 3) .......-0.3V to (VDD + 0.3V) Digital Input Voltage......................-0.3V to (VDD + 0.3V) Digital Output Voltage ................ -0.3V to (OVDD + 0.3V) Power Dissipation .............................................1500mW Operating Temperature Range LTC2242C-10 ........................................... 0C to 70C LTC2242I-10 ........................................-40C to 85C Storage Temperature Range................... -65C to 150C
ORDER INFORMATION
LEAD FREE FINISH LTC2242CUP-10#PBF LTC2242IUP-10#PBF LEAD BASED FINISH LTC2242CUP-10#PBF LTC2242IUP-10#PBF TAPE AND REEL LTC2242CUP-10#TRPBF LTC2242IUP-10#TRPBF TAPE AND REEL LTC2242CUP-10#TR LTC2242IUP-10#TR PART MARKING* LTC2242UP-10 LTC2242UP-10 PART MARKING* LTC2242UP-10 LTC2242UP-10 PACKAGE DESCRIPTION 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN PACKAGE DESCRIPTION 64-Lead (9mm x 9mm) Plastic QFN 64-Lead (9mm x 9mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C TEMPERATURE RANGE 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Differential Analog Input (Note 5) Differential Analog Input (Note 6) External Reference CONDITIONS

CONVERTER CHARACTERISTICS
ENC+ 17 ENC- 18 SHDN 19 OE 20 DNC 21 DNC 22 DNC/DB0 23 DNC/DB1 24 OGND 25 OVDD 26 D0-/DB2 27 D0+/DB3 28 D1-/DB4 29 D1+/DB5 30 D2-/DB6 31 D2+/DB7 32
MIN 10 -1 -0.7 -17 -3.5
TYP 0.4 0.2 5 0.7
MAX 1 0.7 17 3.5
UNITS Bits LSB LSB mV %FS
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LTC2242-10
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
PARAMETER Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference SENSE = 1V CONDITIONS MIN TYP 10 60 45 0.18 MAX UNITS V/C ppm/C ppm/C LSBRMS
CONVERTER CHARACTERISTICS
ANALOG INPUT The denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25C. (Note 4)
SYMBOL VIN VIN, CM IIN ISENSE IMODE ILVDS tAP tJITTER PARAMETER Analog Input Range (AIN+ - AIN-) Analog Input Common Mode (AIN+ + AIN-)/2 Analog Input Leakage Current SENSE Input Leakage MODE Pin Pull-Down Current to GND LVDS Pin Pull-Down Current to GND Sample and Hold Acquisition Delay Time Sample and Hold Acquisition Delay Time Jitter Full Power Bandwidth Figure 8 Test Circuit CONDITIONS 2.375V < VDD < 2.625V (Note 7) Differential Input (Note 7) 0 < AIN+, AIN- < VDD 0V < SENSE < 1V

MIN 1.2 -1 -1
TYP 0.5 to 1 1.25
MAX 1.3 1 1
UNITS V V A A A A ns fsRMS MHz
7 7 0.4 95 1200
DYNAMIC ACCURACY
SYMBOL SNR PARAMETER
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. AIN = -1dBFS. (Note 4)
CONDITIONS 10MHz Input 70MHz Input 140MHz Input 240MHz Input SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic (Note 11) 10MHz Input 70MHz Input 140MHz Input 240MHz Input Spurious Free Dynamic Range 4th Harmonic or Higher (Note 11) 10MHz Input 70MHz Input 140MHz Input 240MHz Input S/(N+D) Signal-to-Noise Plus Distortion Ratio (Note 12) 10MHz Input 70MHz Input 140MHz Input 240MHz Input IMD Intermodulation Distortion fIN1 = 135MHz, fIN2 = 140MHz
l l l l
MIN 59.2
TYP 60.6 60.5 60.5 60.4 78
MAX
UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBc
Signal-to-Noise Ratio (Note 10)
63
75 74 73 85
71
85 85 85 60.4
58.2
60.4 60.3 60.2 81
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LTC2242-10 INTERNAL REFERENCE CHARACTERISTICS
PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance 2.375V < VDD < 2.625V -1mA < IOUT < 1mA CONDITIONS IOUT = 0
(Note 4)
MIN 1.225 TYP 1.25 35 3 2 MAX 1.275 UNITS V ppm/C mV/V
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL VID VICM RIN CIN VIH VIL IIN CIN OVDD = 2.5V COZ ISOURCE ISINK VOH VOL OVDD = 1.8V VOH VOL VOD VOS High Level Output Voltage Low Level Output Voltage Differential Output Voltage Output Common Mode Voltage IO = -500A IO = 500A Hi-Z Output Capacitance Output Source Current Output Sink Current High Level Output Voltage Low Level Output Voltage OE = High (Note 7) VOUT = 0V VOUT = 2.5V IO = -10A IO = -500A IO = 10A IO = 500A PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance (Note 7) VDD = 2.5V VDD = 2.5V VIN = 0V to VDD (Note 7) CONDITIONS (Note 7) ENCODE INPUTS (ENC +, ENC -)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
MIN

TYP
MAX
UNITS V
0.2 1.2 1.5 1.5 4.8 2 2.0
Internally Set Externally Set (Note 7)
V V k pF V
LOGIC INPUTS (OE, SHDN)

1.7 0.7 -10 3 10
V A pF
LOGIC OUTPUTS (CMOS MODE) 3 37 23 2.495 2.45 0.005 0.07 1.75 0.07

pF mA mA V V V V V V 454 1.375 mV V
LOGIC OUTPUTS (LVDS MODE) 100 Differential Load 100 Differential Load 247 1.125 350 1.250
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LTC2242-10 POWER REQUIREMENTS
SYMBOL VDD PSLEEP PNAP OVDD IVDD IOVDD PDISS OVDD IVDD PDISS PARAMETER Analog Supply Voltage Sleep Mode Power Nap Mode Power Output Supply Voltage Analog Supply Current Output Supply Current Power Dissipation Output Supply Voltage Analog Supply Current Power Dissipation (Note 8) (Note 7)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 9)
CONDITIONS (Note 8) SHDN = High, OE = High, No CLK SHDN = High, OE = Low, No CLK (Note 8)

MIN 2.375
TYP 2.5 1 28
MAX 2.625
UNITS V mW mW
LVDS OUTPUT MODE 2.375 2.5 285 58 858 0.5 2.5 285 740 2.625 320 70 975 2.625 320 V mA mA mW V mA mW
CMOS OUTPUT MODE
TIMING CHARACTERISTICS
SYMBOL fS tL tH tAP tOE tD tC PARAMETER Sampling Frequency ENC Low Time (Note 7) ENC High Time (Note 7) Sample-and-Hold Aperture Delay Output Enable Delay ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Rise Time Fall Time Pipeline Latency CMOS OUTPUT MODE tD tC Pipeline Latency ENC to DATA Delay ENC to CLKOUT Delay DATA to CLKOUT Skew Full Rate CMOS Demuxed Interleaved Demuxed Simultaneous
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On

MIN 1 1.9 1.5 1.9 1.5
TYP 2 2 2 2 0.4
MAX 250 500 500 500 500
UNITS MHz ns ns ns ns ns
(Note 7) (Note 7) (Note 7) (tC - tD) (Note 7)

5 1 1 -0.6 1.7 1.7 0 0.5 0.5 5
10 2.8 2.8 0.6
ns ns ns ns ns ns Cycles
LVDS OUTPUT MODE
(Note 7) (Note 7) (tC - tD) (Note 7)

1 1 -0.6
1.7 1.7 0 5 5 5 and 6
2.8 2.8 0.6
ns ns ns Cycles Cycles Cycles
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LTC2242-10 ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 2.5V, fSAMPLE = 250MHz, LVDS outputs, differential ENC+/ENC- = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 5: Integral nonlinearity is defined as the deviation of a code from a "best straight line" fit to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from -0.5 LSB when the output code flickers between 00 0000 0000 and 11 1111 1111 in 2's complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. Note 9: VDD = 2.5V, fSAMPLE = 250MHz, differential ENC+/ENC- = 2VP-P sine wave, input range = 1VP-P with differential drive, output CLOAD = 5pF. Note 10: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dB lower. Note 11: SFDR minimum values are for LVDS mode. Typical values are for both LVDS and CMOS modes. Note 12: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dB lower.
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25C unless otherwise noted, Note 4)
Integral Nonlinearity
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 256 512 OUTPUT CODE 768 1024
224210 G01
Differential Nonlinearity
1.0 0.8 0.6 AMPLITUDE (dB) 1024
224210 G02
8192 Point FFT, fIN = 5MHz, -1dB, 2V Range, LVDS Mode
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 256 512 OUTPUT CODE 768
0
20
40 60 80 FREQUENCY (MHz)
100
120
224210 G03
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LTC2242-10 TYPICAL PERFORMANCE CHARACTERISTICS
8192 Point FFT, fIN = 70MHz, -1dB, 2V Range, LVDS Mode
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 0 20 40 60 80 FREQUENCY (MHz) 100 120
224210 G04
(TA = 25C unless otherwise noted, Note 4) 8192 Point FFT, fIN = 240MHz, -1dB, 2V Range, LVDS Mode
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110
8192 Point FFT, fIN = 140MHz, -1dB, 2V Range, LVDS Mode
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 0 20 40 60 80 FREQUENCY (MHz) 100 120
224210 G05
0
20
40 60 80 FREQUENCY (MHz)
100
120
224210 G06
8192 Point FFT, fIN = 500MHz, -1dB, 1V Range, LVDS Mode
0 -10 -20 -30 AMPLITUDE (dB) AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 0 20 40 60 80 FREQUENCY (MHz) 100 120
224210 G07
8192 Point FFT, fIN = 1GHz, -1dB, 1V Range, LVDS Mode
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 20 40 60 80 FREQUENCY (MHz) 100 120
224210 G08
8192 Point 2-Tone FFT, fIN = 135MHz and 140MHz, -1dB, 2V Range, LVDS Mode
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 -60 -70 -80 -90 -100 -110 0 20 40 60 80 FREQUENCY (MHz) 100 120
224210 G09
SNR vs Input Frequency, -1dB, LVDS Mode
62 61 2V RANGE 60 SFDR (dBFS) SNR (dBFS) 85 80 75
SFDR (HD2 and HD3) vs Input Frequency, -1dB, LVDS Mode
95 90 85 SFDR (dBFS) 80 75 70 65 60
SFDR (HD4+) vs Input Frequency, -1dB, LVDS Mode
70 65 1V RANGE 60 2V RANGE 55 50
1V RANGE 2V RANGE
59 58 57 56 55 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
224210 G10
1V RANGE
45 40 0 100 200 300 400 500 600 700 800 900 1000 INPUT FREQUENCY (MHz)
224210 G11
0 100 200 300 400 500 600 700 800 9001000 INPUT FREQUENCY (MHz)
224210 G12
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LTC2242-10 TYPICAL PERFORMANCE CHARACTERISTICS
SFDR and SNR vs Sample Rate, 2V Range, fIN = 30MHz, -1dB, LVDS Mode
90 85 SFDR AND SNR (dBFS) 80 75 70 65 SNR 60 55 0 50 150 200 100 SAMPLE RATE (Msps) 250 90 80 SFDR SFDR (dBc AND dFBS) 70 60 SNR (dBFS) 50 40 30 20 10 300 0 -50 -40 -20 -30 -10 INPUT LEVEL (dBFS) 0
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(TA = 25C unless otherwise noted, Note 4)
SFDR vs Input Level, fIN = 70MHz, 2V Range
61.0 dBFS 60.5 60.0 59.5 59.0 58.5 58.0
SNR vs SENSE, fIN = 5MHz, -1dB
dBc
57.5 0.5
0.6
0.7
0.8
0.9
1
224210 G15
SENSE PIN (V)
224210 G13
IVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB
300 290 IVDD (mA) 280 2V RANGE 1V RANGE 260 250 240 230 220 0 50 200 150 SAMPLE RATE (Msps) 100 250
224210 G16
IOVDD vs Sample Rate, 5MHz Sine Wave Input, -1dB
60 50 40 IOVDD (mA) 30 20 10 0 LVDS OUTPUTS OVDD = 2.5V
270
CMOS OUTPUTS OVDD = 1.8V
0
50
100 150 200 SAMPLE RATE (Msps)
250
224210 G17
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LTC2242-10 PIN FUNCTIONS
(CMOS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN - (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1F ceramic chip capacitor, to Pins 11, 12 with a 2.2F ceramic capacitor and to ground with 1F ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1F ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1F ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1F ceramic chip capacitor, to Pins 5, 6 with a 2.2F ceramic capacitor and to ground with 1F ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1F ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC - (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1F ceramic for single-ended encode signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. DNC (Pins 21, 22, 40, 43): Do not connect these pins. DB0-DB9 (Pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): Digital Outputs, B Bus. DB9 is the MSB. At high impedance in full rate CMOS mode. OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1F ceramic chip capacitor.
OFB (Pin 37): Over/Under Flow Output for B Bus. High when an over or under flow has occurred. At high impedance in full rate CMOS mode. CLKOUTB (Pin 38): Data Valid Output for B Bus. In demux mode with interleaved update, latch B bus data on the falling edge of CLKOUTB. In demux mode with simultaneous update, latch B bus data on the rising edge of CLKOUTB. This pin does not become high impedance in full rate CMOS mode. CLKOUTA (Pin 39): Data Valid Output for A Bus. Latch A bus data on the falling edge of CLKOUTA. DA0-DA9 (Pins 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): Digital Outputs, A Bus. DA9 is the MSB. OFA (Pin 56): Over/Under Flow Output for A Bus. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2's complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2's complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a 0.5V input range. Connecting SENSE to VDD selects the internal reference and a 1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of VSENSE. 1V is the largest valid input range. VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2F ceramic chip capacitor. GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.
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LTC2242-10 PIN FUNCTIONS
(LVDS Mode)
AIN+ (Pins 1, 2): Positive Differential Analog Input. AIN- (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1F ceramic chip capacitor, to Pins 11, 12 with a 2.2F ceramic capacitor and to ground with 1F ceramic capacitor. REFLB (Pins 7, 8): ADC Low Reference. Bypass to Pins 5, 6 with 0.1F ceramic chip capacitor. Do not connect to Pins 11, 12. REFHB (Pins 9, 10): ADC High Reference. Bypass to Pins 11, 12 with 0.1F ceramic chip capacitor. Do not connect to Pins 5, 6. REFLA (Pins 11, 12): ADC Low Reference. Bypass to Pins 9, 10 with 0.1F ceramic chip capacitor, to Pins 5, 6 with a 2.2F ceramic capacitor and to ground with 1F ceramic capacitor. VDD (Pins 13, 14, 15, 62, 63): 2.5V Supply. Bypass to GND with 0.1F ceramic chip capacitors. GND (Pins 16, 61, 64): ADC Power Ground. ENC+ (Pin 17): Encode Input. Conversion starts on the positive edge. ENC- (Pin 18): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1F ceramic for single-ended encode signal. SHDN (Pin 19): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 20): Output Enable Pin. Refer to SHDN pin function. DNC (Pins 21, 22, 23, 24): Do not connect these pins. D0-/D0+ to D9-/D9+ (Pins 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): LVDS Digital Outputs. All LVDS outputs require differential 100 termination resistors at the LVDS receiver. D9-/D9+ is the MSB.
OGND (Pins 25, 33, 41, 50): Output Driver Ground. OVDD (Pins 26, 34, 42, 49): Positive Supply for the Output Drivers. Bypass to ground with 0.1F ceramic chip capacitor. CLKOUT-/CLKOUT+ (Pins 35 to 36): LVDS Data Valid Output. Latch data on rising edge of CLKOUT-, falling edge of CLKOUT+. OF-/OF+ (Pins 55 to 56): LVDS Over/Under Flow Output. High when an over or under flow has occurred. LVDS (Pin 57): Output Mode Selection Pin. Connecting LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3VDD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3VDD selects demux CMOS mode with interleaved update. Connecting LVDS to VDD selects LVDS mode. MODE (Pin 58): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and turns the clock duty cycle stabilizer off. Connecting MODE to 1/3VDD selects offset binary output format and turns the clock duty cycle stabilizer on. Connecting MODE to 2/3VDD selects 2's complement output format and turns the clock duty cycle stabilizer on. Connecting MODE to VDD selects 2's complement output format and turns the clock duty cycle stabilizer off. SENSE (Pin 59): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a 0.5V input range. Connecting SENSE to VDD selects the internal reference and a 1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of VSENSE. 1V is the largest valid input range. VCM (Pin 60): 1.25V Output and Input Common Mode Bias. Bypass to ground with 2.2F ceramic chip capacitor. GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground.
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LTC2242-10 FUNCTIONAL BLOCK DIAGRAM
AIN+ INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND VDD
AIN-
VCM 2.2F
1.25V REFERENCE RANGE SELECT SHIFT REGISTER AND CORRECTION
SENSE
REF BUF
REFH
REFL
INTERNAL CLOCK SIGNALS OVDD
DIFF REF AMP
DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER
CONTROL LOGIC
OUTPUT DRIVERS
* * *
+ OF - + D9 - + - + -
D0 CLKOUT
REFLB REFHA 2.2F 0.1F 1F
REFLA REFHB 0.1F 1F ENC+ ENC- M0DE LVDS SHDN OE
224210 F01
OGND
Figure 1. Functional Block Diagram
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LTC2242-10 TIMING DIAGRAMS
LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels
tAP ANALOG INPUT N tH tL ENC- ENC+ tD D0-D9, OF tC N-5 N-4 N-3 N-2 N-1 N+1 N+2 N+3 N+4
CLKOUT- CLKOUT+
224210 TD01
Full-Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N tH tL ENC- ENC+ tD DA0-DA9, OFA tC CLKOUTB CLKOUTA N-5 N-4 N-3 N-2 N-1 N+1 N+2 N+3 N+4
DB0-DB9, OFB
HIGH IMPEDANCE
224210 TD02
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12
LTC2242-10 TIMING DIAGRAMS
Demultiplexed CMOS Outputs with Interleaved Update All Outputs Are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N tH tL ENC- ENC+ tD DA0-DA9, OFA N-5 tD DB0-DB9, OFB N-6 tC CLKOUTB CLKOUTA
224210 TD03
N+2 N+3 N+1
N+4
N-3
N-1
N-4 tC
N-2
Demultiplexed CMOS Outputs with Simultaneous Update All Outputs Are Single-Ended and Have CMOS Levels
tAP ANALOG INPUT N tH tL ENC- ENC+ tD DA0-DA9, OFA tD DB0-DB9, OFB tC CLKOUTB CLKOUTA
224210 TD04
N+2 N+3 N+1
N+4
N-6
N-4
N-2
N-5
N-3
N-1
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13
LTC2242-10 APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log Full Power Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC- voltage to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = -20log (2 * fIN * tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2242-10 is a CMOS pipelined multi-step converter. The converter has five pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal performance the analog inputs should be driven differentially. The encode input is differential for improved common mode noise immunity. The LTC2242-10 has two phases of operation, determined by the state of the differential ENC+/ENC- input pins. For brevity, the text will refer to ENC+ greater than ENC- as ENC high and ENC+ less than ENC- as ENC low. 2fa + fb, 2fb + fa, 2fa - fb and 2fb - fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal.
( V2 + V3 + V4 + ...Vn )/ V1
2 2 2 2
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are
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14
LTC2242-10 APPLICATIONS INFORMATION
Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the "Input S/H" shown in the block diagram. At the instant that ENC transitions from low to high, the sampled input is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes back high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2242-10 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input
LTC2242-10 VDD 10 CPARASITIC 1.8pF RON 14 CPARASITIC 1.8pF VDD CSAMPLE 2pF RON 14 CSAMPLE 2pF
AIN+
VDD 10
AIN-
1.5V 6k ENC+ ENC- 6k 1.5V
224210 F02
Figure 2. Equivalent Input Circuit
voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing 0.5V for the 2V range or 0.25V for the 1V range, around a common mode voltage of 1.25V. The VCM output pin (Pin 60) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential
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15
LTC2242-10 APPLICATIONS INFORMATION
driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2F or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2242-10 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC, the sample-and-hold circuit will connect the 2pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2fS); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100 or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2242-10 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100 for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain
ANALOG INPUT 0.1F
bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a capacitively-coupled input circuit. The impedance seen by the analog inputs should be matched. The 25 resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from
10 VCM 2.2F 0.1F ANALOG INPUT T1 1:1 25 25 25 0.1F AIN+ AIN+ 12pF 25 AIN- AIN-
224210 F03
LTC2242-10
T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 3. Single-Ended to Differential Conversion Using a Transformer
50 HIGH SPEED DIFFERENTIAL AMPLIFIER VCM 2.2F 25 3pF AIN+ AIN+ 12pF LTC2242-10
+
CM
+ -
-
25 3pF
AIN- AIN-
224210 F04
Figure 4. Differential Drive with an Amplifier
VCM 100 0.1F 100 25 2.2F AIN+ AIN+ ANALOG INPUT 0.1F 25 12pF AIN- AIN-
224210 F05
LTC2242-10
Figure 5. Capacitively-Coupled Drive
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LTC2242-10 APPLICATIONS INFORMATION
the sample-and-hold charging glitches and limiting the wideband noise at the converter input. For input frequencies higher than 100MHz, the capacitor may need to be decreased to prevent excessive signal loss. The AIN+ and AIN- inputs each have two pins to reduce package inductance. The two AIN+ and the two AIN- pins should be shorted together. For input frequencies above 100MHz the input circuits of Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.25V. In Figure 8 the series inductors are impedance matching elements that maximize the ADC bandwidth. Reference Operation Figure 9 shows the LTC2242-10 reference circuitry consisting of a 1.25V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (1V differential) or 1V (0.5V differential). Tying the SENSE pin to VDD selects the 2V range; typing the SENSE pin to VCM selects the 1V range. The 1.25V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.25V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has four pins: two each of REFHA and REFHB for the high reference and two each of REFLA and REFLB for the low reference. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 9.
0.1F ANALOG INPUT 25 T1 0.1F 25 AIN- AIN- T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
224210 F07
10
VCM 2.2F
0.1F ANALOG INPUT 25 T1 0.1F 25
12 0.1F
AIN+ AIN+ 8pF AIN- AIN- LTC2242-10
12
T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
224210 F06
Figure 6. Recommended Front End Circuit for Input Frequencies Between 100MHz and 250MHz
10
VCM 2.2F AIN+
0.1F
AIN+
LTC2242-10
Figure 7. Recommended Front End Circuit for Input Frequencies Between 250MHz and 500MHz
10
VCM 2.2F
0.1F ANALOG INPUT 25 T1 0.1F 25
2.7nH 0.1F
AIN+ AIN+ AIN- AIN- LTC2242-10
2.7nH
T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
224210 F08
Figure 8. Recommended Front End Circuit for Input Frequencies Above 500MHz
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LTC2242-10 APPLICATIONS INFORMATION
LTC2242-10 1.25V VCM 2.2F 1V RANGE DETECT AND CONTROL SENSE REFLB 0.1F REFHA BUFFER INTERNAL ADC HIGH REFERENCE 0.5V 2 1.25V BANDGAP REFERENCE
the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1F ceramic capacitor. Input Range
TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 * VSENSE FOR 0.5V < VSENSE < 1V 1F
The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 1.7dB. See the Typical Performance Characteristics section. Driving the Encode Inputs The noise performance of the LTC2242-10 can depend on the encode signal quality as much as on the analog input. The ENC+/ENC- inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 4.8k resistor to a 1.5V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter.
2.2F DIFF AMP 1F REFLA 0.1F REFHB INTERNAL ADC LOW REFERENCE
224210 F09
Figure 9. Equivalent Reference Circuit
1.25V 8k 0.75V 12k
VCM 2.2F SENSE 1F LTC2242-10
In applications where jitter is critical (high input frequencies) take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to 2.0V. Each input may be driven from ground to VDD for single-ended drive.
224210 F10
Figure 10. 1.5V Range ADC
Other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to SENSE. It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If
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LTC2242-10 APPLICATIONS INFORMATION
LTC2242-10 VDD TO INTERNAL ADC CIRCUITS 1.5V BIAS 4.8k ENC+ 50 8.2pF 0.1F 50 ENC- 0.1F 100 VDD 1.5V BIAS 4.8k
CLOCK INPUT
T1 MA/COM 0.1F ETC1-1-13
VDD
*
*
224210 F11
Figure 11. Transformer Driven ENC+/ENC-
VTHRESHOLD = 1.5V
ENC+ 1.5V ENC- LTC2242-10 0.1F
224210 F12a
0.1F LVDS CLOCK
ENC+ LTC2242-10
100 0.1F
ENC-
224210 F12b
Figure 12a. Single-Ended ENC Drive, Not Recommended for Low Jitter
Figure 12b. ENC Drive Using LVDS
Maximum and Minimum Encode Rates The maximum encode rate for the LTC2242-10 is 250Msps. For the ADC to operate properly, the encode signal should have a 50% (5%) duty cycle. Each half cycle must have at least 1.9ns for the ADC internal circuitry to have enough settling time for proper operation. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the ENC+ pin to sample the analog input. The falling edge of ENC+ is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2242-10 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2242-10 is 1Msps. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit.
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LTC2242-10 APPLICATIONS INFORMATION
Table 1. Output Codes vs Input Voltage
AIN+ - AIN- (2V Range) >+1.000000V +0.998047V +0.996094V +0.001953V 0.000000V -0.001953V -0.003906V -0.998047V -1.000000V <-1.000000V OF 1 0 0 0 0 0 0 0 0 1 D9 - D0 (Offset Binary) 11 1111 1111 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 01 1111 1110 00 0000 0001 00 0000 0000 00 0000 0000 D9 - D0 (2's Complement) 01 1111 1111 01 1111 1111 01 1111 1110 00 0000 0001 00 0000 0000 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 10 0000 0000
Digital Output Buffers (CMOS Modes) Figure 13a shows an equivalent circuit for a single output buffer in the CMOS output mode. Each buffer is powered by OVDD and OGND, which are isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to voltages as low as 0.5V. The internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2242-10 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 74VCX245 CMOS latch. For full speed operation the capacitive load should be kept under 10pF . Lower OVDD voltages will also help reduce interference from the digital outputs. Digital Output Buffers (LVDS Mode) Figure 13b shows an equivalent circuit for a differential output pair in the LVDS output mode. A 3.5mA current is steered from OUT+ to OUT- or vice versa which creates a 350mV differential voltage across the 100 termination resistor at the LVDS receiver. A feedback loop regulates the common mode output voltage to 1.25V. For proper operation each LVDS output pair needs an external 100 termination resistor, even if the signal is not used (such as OF+/OF- or CLKOUT+/CLKOUT-). To minimize noise the PC board traces for each LVDS output pair should be routed close together. To minimize clock skew all LVDS PC board traces should have about the same length.
Digital Output Modes The LTC2242-10 can operate in several digital output modes: LVDS, CMOS running at full speed, and CMOS demultiplexed onto two buses, each of which runs at half speed. In the demultiplexed CMOS modes the two buses (referred to as bus A and bus B) can either be updated on alternate clock cycles (interleaved mode) or simultaneously (simultaneous mode). For details on the clock timing, refer to the timing diagrams. The LVDS pin selects which digital output mode the part uses. This pin has a four-level logic input which should be connected to GND, 1/3VDD, 2/3VDD or VDD. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the LVDS pin.
Table 2. LVDS Pin Function
LVDS GND 1/3VDD 2/3VDD VDD DIGITAL OUTPUT MODE Full-Rate CMOS Demultiplexed CMOS, Simultaneous Update Demultiplexed CMOS, Interleaved Update LVDS
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LTC2242-10 APPLICATIONS INFORMATION
LTC2242-10 OVDD VDD VDD 0.5V TO 2.625V 0.1F OVDD DATA FROM LATCH OE OGND 3.5mA
224210 F13a
LTC2242-10
OVDD 2.5V 0.1F
D - 43 TYPICAL DATA OUTPUT 10k 1.25V D 10k
D OUT+ 100 OUT- D LVDS RECEIVER
PREDRIVER LOGIC
+
OGND
Figure 13a. Digital Output Buffer in CMOS Mode
224210 F13b
Figure 13b. Digital Output in LVDS Mode
Data Format The LTC2242-10 parallel digital output can be selected for offset binary or 2's complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2's complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 3 shows the logic states for the MODE pin.
Table 3. MODE Pin Function
MODE PIN 0 1/3VDD 2/3VDD VDD OUTPUT FORMAT Offset Binary Offset Binary 2's Complement 2's Complement CLOCK DUTY CYCLE STABILIZER Off On On Off
to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. In all CMOS modes, A bus data will be updated just after CLKOUTA rises and can be latched on the falling edge of CLKOUTA. In demux CMOS mode with interleaved update, B bus data will be updated just after CLKOUTB rises and can be latched on the falling edge of CLKOUTB. In demux CMOS mode with simultaneous update, B bus data will be updated just after CLKOUTB falls and can be latched on the rising edge of CLKOUTB. In LVDS mode, data will be updated just after CLKOUT+/CLKOUT- rises and can be latched on the falling edge of CLKOUT+/CLKOUT-. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply then OVDD should be tied to that same 1.8V supply. In the CMOS output mode, OVDD can be powered with any voltage up to 2.625V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. In the LVDS output mode, OVDD should be connected to a 2.5V supply and OGND should be connected to GND.
224210fc
Overflow Bit An overflow output bit indicates when the converter is overranged or underranged. In CMOS mode, a logic high on the OFA pin indicates an overflow or underflow on the A data bus, while a logic high on the OFB pin indicates an overflow or underflow on the B data bus. In LVDS mode, a differential logic high on the OF+/OF- pins indicates an overflow or underflow. Output Clock The ADC has a delayed version of the ENC+ input available as a digital output, CLKOUT. The CLKOUT pin can be used
21
LTC2242-10 APPLICATIONS INFORMATION
Output Enable The outputs may be disabled with the output enable pin, OE. In CMOS or LVDS output modes OE high disables all data outputs including OF and CLKOUT. The data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. The output Hi-Z state is intended for use during long periods of inactivity. The Hi-Z state is not a truly open circuit; the output pins that make an LVDS output pair have a 20k resistance between them. Therefore in the CMOS output mode, adjacent data bits will have 20k resistance in between them, even in the Hi-Z state. Sleep and Nap Modes The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 28mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep and nap mode all digital outputs are disabled and enter the Hi-Z state. GROUNDING AND BYPASSING The LTC2242-10 requires a printed circuit board with a clean unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital signal alongside an analog signal or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and REFLA. These capacitors should be as close to the device as possible (1.5mm or less). Size 0402 ceramic capacitors are recommended. The 2.2F capacitor between REFHA and REFLA can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2242-10 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. HEAT TRANSFER Most of the heat generated by the LTC2242-10 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area. Clock Sources for Undersampling Undersampling is especially demanding on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. A clock source that degrades SNR of a full-scale signal by 1dB at 70MHz will degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz. In cases where absolute clock frequency accuracy is relatively unimportant and only a single ADC is required, a canned oscillator from vendors such as Saronix or Vectron can be placed close to the ADC and simply connected directly to the ADC. If there is any distance to the ADC, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. You must not allow the clock to overshoot the supplies or performance will suffer. Do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise.
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LTC2242-10 APPLICATIONS INFORMATION
The lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a filter close to the ADC may be beneficial. This filter should be close to the ADC to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the ADC. If the circuit is sensitive to close-in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. Even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise from the FPGA disturbing the substrate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing flip-flop as well as the oscillator should be close to the ADC, and powered with a very quiet supply. For cases where there are multiple ADCs, or where the clock source originates some distance away, differential clock distribution is advisable. This is advisable both from the perspective of EMI, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together and distanced from other signals. The differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart.
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Evaluation Circuit Schematic of the LTC2242-10
C25 0.1F C26 0.1F
2.5V R9 12.4 R13 4.99 65 64 61 16 63 62 15 14 13 GND GND GND GND VDD VDD VDD VDD VDD R3 100 4 5 I1N I1P O1N O1P O2N O2P O3N O3P O4N O4P O5N O5P 33 32 35 34 39 38 41 40 43 42 I2N I2P I3N I3P I4N I4P I5N I5P 6 7 R18 100 R19 100 R20 100 R21 100 R22 100 16 17 I6N I6P 31 30 29 28 O8N O8P O6N O6P R28 100 18 19 I7N I7P I8N I8P VBB VE1 VE2 VE3 VE4 VE5 O7N O7P 20 21 24 R30 100 14 15 10 11 8 9 45 44 VC1 VC2 VC3 VC4 VC5 3 22 27 46 13 U3 FINII08 EN12 EN34 EN56 EN78 EN 12 25 26 47 48 3.3V
LTC2242-10
APPLICATIONS INFORMATION
TP6 VCM 2 4 6 25 OGND 33 OGND 41 OGND 50 OGND 26 OVDD 34 OVDD 42 OVDD 49 OVDD SHDN 3 VDD 1 GND 5 4 OE 2 VDD 6 GND
J4 SENSE
2.5V
TP1 EXT REF
TP2 GND R6 1k 2.5V C20 0.1F J2 MODE 1 VDD 3 GND 5 2 4 2/3 6 1/3 R7 1k C22 0.1F C23 0.1F R40 100 R37 BLM18BB470SN1D R43 100 +3.3V R42 100 R39 100 R8 1k C21 0.1F R38 100
C19 0.1F
VC1 VC2 VC3 VC4 VC5
2.5V 1 VCM 3 EXT REF 5
12 25 26 47 48
OF+/OFA OF-/DA9 D9+/DA8 D9-/DA7 D8+/DA6 D8-/DA5 D7+/DA4 D7-/DA3 D6+/DA2 D6-/DA1 D5+/DA0 D5-/DNC D4+/DNC D4-/CLKOUTA D3+/CLKOUTB D3-/OFB CLKOUT+/DB9 CLKOUT-/DB8 D2+/DB7 D2-/DB6 D1+/DB5 D1-/DB4 D0+/DB3 D0-/DB2 DNC/DB1 DNC/DB0 DNC DNC R17 100 3.3V 1 2 23 36 37
C34 0.1F IN U5 SEN 6 5 VO SJ 2 SHDN GND GP 7 GP BYP R25 1k 8
11
3 C24 10F C38 0.01F 3.3V C28 0.1F C29 0.1F C30 0.1F C31 0.1F LVDS BUFFER BYPASS C32 0.1F C33 0.1F C5 0.1F C8 0.1F
ARRAY EEPROM
VERSION DC997B-A DC997B-B DC997B-C DC997B-D DC997B-E DC997B-F 1
DEVICE BITS SAMPLE RATE LTC2242-12 12 250Msps LTC2241-12 12 210Msps LTC2240-12 12 170Msps LTC2242-10 10 250Msps LTC2241-10 10 210Msps LTC2240-10 10 170Msps
1 2 23 36 37
VE1 VE2 VE3 VE4 VE5
24
R23 100 C9 1.8pF LTC2242-12 R14 4.99 R10 12.4 C15 1F R15 49.9 C17 2.2F C16 1F 17 18 ENC+ ENC- VCM 60 C14 0.1F 10 REFHB 9 REFHB 12 REFLA 11 REFLA C13 0.1F 2 1 4 3 6 5 8 7 AIN+ AIN+ AIN- AIN- REFHA REFHA REFLB REFLB 2.5V R24 1k 19 20 59 58 57 SHDN OE SENSE MODE LVDS 56 55 54 53 52 51 48 47 46 45 44 43 40 39 38 37 36 35 32 31 30 29 28 27 24 23 22 21 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 3 22 27 46 13 4 5 6 7 8 9 10 11 14 15 U3 FINII08 EN12 EN34 EN56 EN78 EN I1N I1P I2N I2P I3N I3P I4N I4P I5N I5P 16 17 18 19 +2.5V 2 20 21 24 I6N I6P I7N I7P O1N O1P O2N O2P O3N O3P O4N O4P O5N O5P O6N O6P O7N O7P 45 44 43 42 41 40 39 38 35 34 R16 100k 2.5V R29 4990 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 R46 4990 R26 4990 C27 0.1F 8 33 32 31 30 29 28 I8N I8P VBB O8N O8P VCC 24LC02ST LT1763CDE-2.5 10 IN VO SCL SDA WP A2 A1 A0 GND 4
224210 AI01
J5 SMA
C6 0.1F
T1 MABA-007159-000000
AIN
R11 49.9
C7 0.1F
R12 49.9
R27 49.9
C12 0.1F
C10 0.1F
C18 2.2F
J7 ENCODE C2 CLK 0.1F
T2 MABA-007159-000000
R4 4.99
SMA
R1 49.9
C1 0.1F
R2 49.9
R41 100 C4 1.8pF
C11 0.1F
C3 0.1F
R5 4.99
3.3V TP5 GND TP4 2.5V TP3 (NO TURRET)
J6 AUX PWR CONNECTOR 1 2 3
C36 4.7F
6 5 7 3 2 1
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LTC2242-10 APPLICATIONS INFORMATION
Silkscreen Top Layer 2 GND Plane
Layer 1 Component Side
Layer 3 Power/Ground Plane
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25
LTC2242-10 APPLICATIONS INFORMATION
Layer 4 Power/Ground Planes Layer Back Solder Side
Layer 5 Power/Ground Planes
Silk Screen Back, Solder Side
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26
LTC2242-10 PACKAGE DESCRIPTION
UP Package 64-Lead Plastic QFN (9mm x 9mm)
(Reference LTC DWG # 05-08-1705)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.70 0.05
7.15 0.05 8.10 0.05 9.50 0.05 (4 SIDES)
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE
PACKAGE OUTLINE 0.25 0.05 0.50 BSC 9 .00 0.10 (4 SIDES) 0.75 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP
63 64 0.40 0.10 1 2
PIN 1 TOP MARK (SEE NOTE 5)
PIN 1 CHAMFER
7.15 0.10 (4-SIDES)
(UP64) QFN 1003
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2242-10 RELATED PARTS
PART NUMBER LTC1748 LTC1750 LT(R)1993-2 LT1994 LTC2202 LTC2208 LTC2220 LTC2220-1 LTC2221 LTC2224 LTC2230 LTC2231 LTC2240-10 LTC2240-12 LTC2241-10 LTC2242-12 LTC2242-12 LTC2255 LTC2284 LT5512 LT5514 LT5515 LT5516 LT5517 LT5522 DESCRIPTION 14-Bit, 80Msps, 5V ADC 14-Bit, 80Msps, 5V Wideband ADC High Speed Differential Op Amp Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 12-Bit, 170Msps, 3.3V ADC, LVDS Outputs 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 10-Bit, 170Msps, 3.3V ADC, LVDS Outputs 10-Bit, 135Msps, 3.3V ADC, LVDS Outputs 10-Bit, 170Msps, 2.5V ADC, LVDS Outputs 12-Bit, 170Msps, 2.5V ADC, LVDS Outputs 10-Bit, 210Msps, 2.5V ADC, LVDS Outputs 12-Bit, 210Msps, 2.5V ADC, LVDS Outputs 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs 14-Bit, 125Msps, 3V ADC, Lowest Power 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk DC to 3GHz High Signal Level Downconverting Mixer Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator 40MHz to 900MHz Direct Conversion Quadrature Demodulator 600MHz to 2.7GHz High Linearity Downconverting Mixer COMMENTS 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Up to 500MHz IF Undersampling, 90dB SFDR 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain Low Distortion: -94dBc at 1MHz 150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN 1250mW, 78dB SNR, 100dB SFDR, 48-Pin QFN 890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN 660mW, 67.8dB SNR, 84dB SFDR, 64-Pin QFN 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN 890mW, 61.2dB SNR, 78dB SFDR, 64-Pin QFN 660mW, 61.2dB SNR, 78dB SFDR, 64-Pin QFN 445mW, 60.6dB SNR, 78dB SFDR, 64-Pin QFN 445mW, 65.5dB SNR, 78dB SFDR, 64-Pin QFN 585mW, 60.6dB SNR, 78dB SFDR, 64-Pin QFN 585mW, 65.5dB SNR, 78dB SFDR, 64-Pin QFN 740mW, 65.5dB SNR, 78dB SFDR, 64-Pin QFN 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50 Single-Ended RF and LO Ports
224210fc
28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 1107 REV C * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

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